1. Technical Field of the Invention
This invention most generally relates to data transfer and broadband communication networks within a parallel computing system or a local area network. In particular, the present invention relates to an arrangement of transmitters and receivers and associated fibers for efficient data transfer in a network using fiber optics wherein the fiber optics are bundled and routed for a specific application.
2 Background of the Invention
Technological advancements have dramatically increased the capabilities and possibilities of computing electronics. The increased bandwidth and data transfer rates have resulted in commercial innovation and scientific advancements in many fields. However, data transfer continues to be a bottleneck. This is true for data transfer within an integrated circuit (IC), from one chip to another, from hybrid circuit to hybrid circuit, from integrated circuit board to another integrated circuit board, and from system to system.
Another driving factor leading to ever increasing demands for faster data transfer rates is the need to do tasks that are more complex, requiring multiple computing nodes to cooperate. Digital signal processing, image analysis, and communications technology all require a greater bandwidth. The demand for increased data transfer capability and greater bandwidth translates into increases in both the speed of the data transfer, and the amount of data that is transferred per unit time.
In general, the problems associated with data transfer within an IC and on a system network are similar. With respect to IC""s, increasing the rate of data transfer can be accomplished by increasing the number of data transfer lines and transferring the data in parallel, and/or increasing the transmission speed. There are limitations to the number of I/O lines such as spacing and size requirements, noise problems, reliability of connectors, and the power required to drive multiple lines off-chip. Increasing the transmission speed also has some limitations, as increasing the speed also increases power requirements, introduces timing skew problems across a channel, and usually requires more exotic processing than is standard practice. Combining higher clock speeds and more I/O connections in order to increase bandwidth is exceedingly difficult and impractical using electronics alone.
Using traditional technology, there is a practical upper limit to the number of bit lines that are possible. So long as the technology is based on signals being of an electrical nature, each increase in the number of lines means a corresponding increase in the number of conductors that are required, and the associated problems that are well known in the art.
Due to IC packaging constraints, and problems associated with the connections between the IC substrate and the IC package, there is a limited electronic I/O bandwidth. The most common manufacturing techniques used to interconnect an integrated circuit VLSI die with a package are wire-bonding, flipchip bonding, and tape automated bonding. The maximum clock rate of an I/O pin is typically a few hundred Mbps (millions of bits per second) due to capacitance and inductance and crosstalk associated with the connections between the die and the package. Therefore, the maximum I/O bandwidth of a single IC package is directly proportional to the number of pins times the clock rate per pin. In general, the maximum I/O bandwidth of a packaged IC is typically in the tens of Gigabits/second.
A computer system xe2x80x9cbusxe2x80x9d is an interconnection allowing communication between plug-in modules. The plug-in modules, typically printed circuit boards (PCB), connect to the bus on a backplane printed circuit board. The data transfers are controlled according to the bus protocol. Plug-in modules typically connect to the bus through edge connectors and drive the bus through high power bus transceivers. Various standards define the physical backplane PCB, the mechanical packaging and the bus protocols. There are also a number of bus standards, including PCI, VME, FutureBus+, and Nubus standards.
There are a number of limitations to the bus connection system. In order to transfer data, a plug-in module typically acts as a bus master, and distributed protocols are used to arbitrate between contending plug-in modules and to appoint the bus-master. To actually transfer data, a bus master inserts the information including address information and data in a series of individual word transfers over the bus. Words usually contain 32 bits and the duration of the word transfer is determined by the nature of the bus protocol. Latency in processing the address information and coordinating the transfer to/from the proper devices is a significant problem. If there are more than a few bus masters, contention for the shared resource (the bus) becomes a major problem, resulting in long wait times to gain mastership of the bus.
Also, capacitive loading on a bus due to the plurality of attached modules increases the propagation delay, which also impacts the data transfer rate. Capacitive loading also decreases the impedance of a bus line to a very low value, and results in high currents required to drive the bus at full speed. Improperly terminated bus lines result in multiple reflections of the transmitted signal. The reflections take one or more bus round trip delays to settle, resulting in a settling time delay that is a significant portion of the transfer cycle time for a bus.
The aforementioned problems limit the bandwidth of bus communications. In addition to low bandwidths, electronic busses lack multiple independent channels and cannot provide the parallelism required by large-scale parallel computing and communication systems. The busses are not scalable to interconnect hundreds of plug-in modules since the increasing capacitance, inductance and impedance problems place a limit on the data transfer speed, and the fact that the single channel is shared among many processing modules results in contention for the single xe2x80x9cbottleneckxe2x80x9d resource.
A xe2x80x9clocal area networkxe2x80x9d (LAN) is a means of interconnecting multiple computers. A variety of standards exist, with the most popular perhaps being the family of xe2x80x9cEthernetxe2x80x9d standards (ANSI/IEEE standard 802.3 and others). Like a computer system bus, an Ethernet network consists of a shared medium (coaxial cable) over which all data is transferred. LANs typically have lower bandwidth than system busses, but allow nodes to communicate at larger distances. Several Ethernet standards exist, with data transfer rates of 10 Mbps (millions of bits per second), 100 Mbps and 1 Gbps. Nodes may be separated by distances of up to 100 meters using Ethernet, which is much greater than system bus dimensions that are typically a fraction of a meter.
In recent years, computer system and LAN equipment designers have begun using several techniques for increasing the throughput of data communications. The first is the use of xe2x80x9cswitched networks,xe2x80x9d also called xe2x80x9cswitch fabrics,xe2x80x9d to eliminate the contention for the single shared resource of a bus or shared-medium LAN. The second is the use of fiber optics to increase the clock speed, and hence the throughput, of data transfers.
In a switched network, the single shared medium is replaced by a series of switches that are interconnected with each other and to the computing nodes (the communication endpoints). All these connections are now point-to-point and usually unidirectional, which allows them to be clocked at a higher rate than comparable bussed connections due to lower capacitance and higher impedance, an additional advantage for electronic implementations. The primary advantage of switched networks is that one pair of nodes can communicate simultaneously with a second pair of nodes, as long as the two pairs do not use the same node-to-switch or switch-to-switch connections. Switched fabrics can also scale to hundreds or thousands of nodes, since all connections are point-to-point and capacitance does not grow linearly with the number of nodes.
One problem with switched networks is that some contention may still exist in the network when more than one pair of nodes tries to communicate, since they both may need to use the same switch-to-switch link along their paths. An ideal switched network is called a xe2x80x9ccrossbarxe2x80x9d and consists of a single large switch that connects directly to all nodes in the system, and can provide contention-free communications among them.
A number of switched fabric standards exist now or have been proposed to replace system busses, including Myrinet, RaceWay, the Scalable Coherent Interconnect (SCI), RapidIO, and InfiniBand. These are sometimes called xe2x80x9csystem area networksxe2x80x9d (SANs) or xe2x80x9cstorage area networksxe2x80x9d if used to connect processors to disk drives. Switch fabric standards are also in widespread use for local area networks, including switched Ethernet, Myrinet, and Asynchronous Transfer Mode (ATM).
Traditional crossbar switches allow any combination of ports to connect simultaneously without internal contention. As a result, every connection must have an N2 controller. For example, 16xc3x9716 full-crossbar has 16 input signals and 16 output signals. The 16 output signals are usually to the same 16 hosts, and these output signals have 162 different combinations. Due to the complexity that accompanies the number of ports, and more importantly due to the fact that a large number of signals must fan in or fan out of a single device, it is rare to see a full crossbar larger than 16 ports. In addition, larger crossbar switches are fairly expensive.
A crossbar-switch is an efficient way for electronic equipment to communicate since there is a direct connection between the sender and the receiver. Unfortunately, because every piece of data flows through the switch, a switch failure takes down the entire network. As a result, systems are often built of smaller switches that permit redundancy. However, such redundancy also introduces inefficiencies that are well known and tolerated in the industry.
Typically, crossbar switches require that every port have N pins, where N is at least as wide as the data width (8 bits, for example), but may also including clock and control lines and perhaps separate ground or return lines for each signal. Consequently, a 16xc3x9716 port crossbar-switch with 20 lines per connection will have either 16 or 32 connectors and 640 wires. Increasing this number to a 64xc3x9764 switch with 64 lines each would require 8192 wires, which implies that the ASIC has 8192 pins just for signals. Even if the switch were built of multiple ASICs, the physical space required to attach 64 connectors is significant.
Data transfer protocols are established by a number of standards. These standards all employ standard ways of formatting data in discrete chunks called frames or packets. The packet or frame establishes the format of the data and the various fields and headers are encapsulated and transmitted across a network. A frame or packet usually includes a destination address, control bits for flow control, the data or payload, and error checking in the form of cyclic redundancy checks (CRC) codes or an error correcting code (ECC), as well as headers and trailers to identify the beginning and end of the packet. As information is communicated between devices or systems, the address information is checked by each device or system in the network, and eventually the device of interest receives the data.
Whether transferring data within a circuit or connecting system-to-system, the limited bandwidth of conventional hardware does not satisfy the marketplace. For high data rate transmissions, fiber optics transmit data at Gigabit data rates. Fiber optic communication systems allow information to be transmitted by means of binary digital transmission. The data or information that is to be transmitted is converted into a stream of light pulses, wherein the presence of a pulse corresponds to the transmission of a binary xe2x80x9cone,xe2x80x9d and the absence of light corresponds to the transmission of a binary xe2x80x9czero.xe2x80x9d An optical receiver is used to convert the stream of light pulses into an electrical signal that is processed to determine the transmitted information.
Typically the optical transmitters are light emitting devices such as vertical cavity surface emitting lasers (VCSELS) and light detecting devices such as photodiodes. The optical transmitters and receivers may be encompassed in a separate or fabricated on the same substrate and with accompanying electronics. The fabrication process is well known in the art and U.S. Pat. No. 5,978,401 provides background materials, and is incorporated by reference.
The transmitters have driver circuitry that drives the VCSELS, while the receivers also have receiver circuitry for processing the received signals. The transmitter driver circuitry and the receiver driver circuitry is usually in the form of ASIC devices. The combination of the VCSELS and photodiodes along with the ASIC driver circuitry is called an optical transceiver. One embodiment for hybridization of the transceiver elements is via flip-chip bonding, which is generally explained in U.S. Pat. No. 5,858,814, incorporated by reference herein.
A fiber optic cable is used to transmit the optical data off the transceiver device and mates with the transceiver. A spacing problem exists when there are large arrays of transceivers and corresponding optic cables mating to, each emitter and detector. The coupling and alignment of these multiple fiber optic cables is exceedingly difficult and there is a substantial defect rate in large bundles.
Fiber-optic standards for LANs exist and are in-widespread use today, including the Fiber Distributed Data Interface (FDDI), FibreChannel and several ATM physical layers. Fiber optics are not in widespread use today for system busses, but some standards have been proposed and some prior art exists. Current optical networking systems employ high precision optical mirrors that are used in free-space data transmissions.
Some attempts have been made to address the aforementioned problems. The use of smart pixels to provide the required interconnection has been developed. xe2x80x9cSmart Pixelxe2x80x9d refers to the optical interconnection for digital computing systems such as switching systems and parallel-processor systems. For example, large numbers of optical transmitters and receivers are directly integrated with semiconductor electronic processing elements. The integrated optoelectronic circuits have several benefits., including efficiency of design.
However, there are limitations to the electronic interconnects used in current large scale computing and communication networks. The networks have more bandwidth than a bus by providing multiple independent high bandwidth communication channels. But, the cost of these multiple channels is a large number of electronic wires between cabinets and electronic traces on PCB""s. The inductance and capacitance of these wires and traces necessitates the use of high power transceivers that consume large amounts of power. The inductance and capacitance of these channels also limits the maximum clock rate and the electrical channels are also susceptible to electromagnetic interference (EMI).
There is some prior art that is directed towards changing from metal traces on a backplane PCB to optical paths through free-space or an optical medium. These passive optical busses still suffer from many disadvantages associated with the electronic bus. The optical bus still supports a single communication channel (as in FDDI) so that data transfers still occur sequentially over the bus. The data transfer requires the same steps as in an electrical backplane, where a bus master is first selected and the bus master then broadcasts data over the optical bus which must be received by all plug-in module PCB""s. These PCB""s then perform packet processing to determine whether the packet is addressed to them. This architecture requires that every plug-in module PCB monitors all data on the optical bus. The limitation that every PCB monitor all the data on the optical bus limits the rate at which data is transmitted over the bus to the rate at which every PCB can receive and process the data.
The typical passive optical bus architectures require that optical signals be received on a photodetector array, converted to electronics, and then routed to an electronic IC for further processing. Hence, the peak bandwidth is limited to the peak I/O bandwidth of an electronic integrated circuit, typically tens of Gigabits/second. Thus the passive optical bus is simply a faster version of a conventional electronic bus and it does not provide the high bandwidth required by large-scale computing and communication systems.
Most often, the passive optical technology is used to provide point-to-point high bandwidth connectivity and nothing else. The underlying architecture does not support broadcast channels, one-to-many communications over a single channel, or one-to-all communications over a single channel, simultaneous many-to-many communications over multiple channels. The architecture simply implements multiple passive point-to-point interconnects with no broadcasting. Since this architecture cannot support broadcasting it will have limited use in computing and communications systems which require efficient broadcasting.
Furthermore, the passive optical architecture has power limitations as the number of receivers increases, because the architecture does not allow for the regeneration of optical signals. A fraction of each optical signal is delivered to each photodetector receiver through the use of partially reflective micromirrrors. This free-space technique allows an optical signal to be delivered to a small number of receivers, but it cannot be used to interconnect a large number of receivers since the original optical signal can only pass through a limited number of partially reflective mirrors before the signal is lost.
Overall, the complexity and cost of the prior art systems is delaying large-scale integration. Thus, there is a need for increased system bandwidth through both increased data rates and improved mechanical and electrical interconnects, that is robust, easier to manufacture, and cost-effective.
Latency is the amount of time it takes for data to be sent from a source node to a destination node. One of the key impediments to significantly increasing the speed with which communications devices can communicate with one another is the very limited capability of existing systems to transfer data in parallel. Another impediment is the need for reading and interpreting the address of each data packet, whether or not the data is intended for that particular device. The process of reading and interpreting packet destination addresses is done at each device in the network, and results in a dramatic limitation in the speed of data transfer within the network.
Although some researchers have demonstrated Terabits/s serial connection, the methodology is overly complex and the price and size of these systems is impractical for system area networks. Recent innovations have permitted wavelength division multiplexing (WDM) systems to increase their bandwidth considerably, however, this is primarily a telecommunications (wide-area networkingxe2x80x94WAN) solution. WDM systems are still relatively large and expensive, but compared to laying new fibers across the country the cost of the transmitters and receivers seems insignificant. For a local area network (LAN) or system area networks (SANs), WDM is generally cost-prohibitive and often will not meet form-fit-factors requirements. For LANs/SANs, the problems preventing effective wide bandwidth are: connector size and reliability, channel skew, wire impedance, and power dissipation.
Various methods have been proposed for increasing the data throughput at each node of a network. Optoelectronic methods offer the widest bandwidth at this time. There has been some work incorporating optoelectronic circuits using III-V technology onto complimentary metal-oxide-semiconductor (CMOS) structures in silicon. Though this so-called hybridization method leads to vastly increased bandwidths numerous challenges remain. One of them deals with the differing types of network architectures that are used, and the differing amounts of signal processing that is required while routing signals within a node and from node to node. In particular, the issue of efficiently coupling data into and out of a chip in a way that facilitates the fabrication and use of the technology has arisen.
Several interconnection methods, e.g. ring, star, mesh, etc., are in common usage. An optimum configuration for one method may not be best suited for other methods. For example, some nodes and data streams require more processing or conditioning of data, while other have little or no processing.
There are a number of possibilities for routing signals through a node. At one end of the spectrum are signals that are simply re-routed with little or no signal processing. At the other extreme are signals that require significant amounts of signal processing. There is a significant difference in the requirements of peripheral hardware and software for routing these two extremes of signals in and out of a node.
A method for accomplishing the distribution of signals is known as a router or hub. These components are bulky and consist of many parts. In hubs currently available, there are single fibers from which optical signals are converted into electrical signals that are then brought in to a central processing unit (CPU) and then rerouted and sent to other separate lasers for retransmission. This process is cumbersome and inefficient.
Ideally, what is needed is a network with wide channels, fast links, small and reliable connectors, low power, low latency, and minimal impact on higher-level communication protocols. What is needed is a way of accommodating a broader range of interconnection topologies without increasing the complexity of manufacturing them. What is needed is a way of handling such diverse requirements that does not increase manufacturing complexity. What is needed is a way of reducing the bulk and complexity of present systems and avoiding the problems associated with optical mirrors. What is needed is a way to simplify the number of fibers connecting nodes. What is needed is a means for reducing the latency so that it is not a significant factor in limiting data transfer. In other words, what is needed is a way of transferring data from one node in a network to any other node in the network in a bit-parallel manner in such a way that each intervening node that touches the data (whether switch or network interface is controllerxe2x80x94NIC) minimizes the time required to process data through.
The present invention is an apparatus for communicating data on and off an integrated circuit or chip in a network node. In one embodiment the chip has a silicon substrate, and has peripheral components implemented using CMOS technology. The CMOS circuitry facilitates the transfer of incoming data (from the node itself or from another node) to other nodes. The arrangement of the transmitters and receivers along with associated circuitry is done to optimize the network topology.
This invention pertains to methods of grouping or bundling the transmitters and receivers, and of the optical fibers used to communicate the data. In particular, it involves the arrangement of the optical transmitters and receivers that are used in optoelectronic circuits so that signals can be routed most efficiently for a given network topology. The network topologies include ring, star, routers, and crossbars. Depending on design parameters, some signals require very little signal processing while other signals require a substantial amount. At one extreme, little additional signal processing is required; the signal is simply re-routed out of the chip. For this type of arrangement the transmitters and receivers can be paired together in a close relationship, such as interdigitated. In other cases, it is necessary to reprocess the data, e.g. apply error correction techniques, prior to re-transmitting it. This requires more processing circuitry, and having the transmitters separate from the receivers allows more room for circuitry.
In one embodiment, the transceiver pairs are interdigitated, meaning that columns of transmitters and receivers are located side by side. The optical fibers, i.e., the means of coupling the signals on and off the chip, are connected to the transceiver pair. The interdigitated transceivers provides a highly efficient and compact network topology due to the close proximity of the transmitter and receiver pairs.
Interdigitated transceivers are appropriate when there is minimal signal processing required before retransmitting the data, because the extent of the data processing is limited by the available space. Using present standards, the constraints on the pitch of the transmitter-receiver pairs are due to thermal dissipation requirements and the need for providing means for supplying power to large numbers of transceivers. The pitch is currently 125 microns, though it is expected that it will be reduced as the technology advances. Thus, the minimum area for any associated peripheral CMOS circuitry is 125xc3x97125 microns squared. This relatively small amount of area leaves little room for sophisticated on-chip signal processing a few hundred logic gates at most. A noise issue must also be addressed since there are digital logic devices operating inside an analog portion of chip. For signals that do not require significant amounts of signal processing, this approach works well. This embodiment provides bidirectional signal pairs for full-duplex communication between connected nodes.
One advantage of the present invention is that it enables high density, high bandwidth interconnects between network nodes. Another advantage of this invention is that it enables increased connectivity of the network and a reduction in size of the routing capability.
An object of this invention is an apparatus for sending and receiving data in a network that includes a silicon substrate, peripheral CMOS circuitry, transmitters and receivers for the data, and optical communication means to communicate the data from the network node. Furthermore, the optical communication means connected to the transmitters may be bundled together and the optical communication means connected to the receivers may be bundled together. One object of this invention includes where the transmitters are grouped together. A further object of this invention also includes where the receivers are grouped together.
Yet a further object of this invention is an apparatus that allows diverse network topologies such as ring, star, mesh, and crossbar to communicate among and between each other with simple processing.
An additional object of this invention is a means for connecting one or more fibers in bundles to a single substrate, whereby the substrate contains digital logic capability to perform data processing.
Another object of this invention is the ability of bringing together multiple fiber bundles into individual transceiver chips for complicated network architectures. Such a system may also provide interconnections consisting of multiple, bidirectional fiber bundles to create higher-level network topologies.
In one embodiment of this invention the fibers are clustered, so all of the fibers are brought into a single chip. Thus, a transceiver is now a hub or router. In contrast, existing routers and hubs normally contain transceiver chips with discrete transceiver chips for each channel.
The IC of the present invention are transceiver chips so that different fibers carry information to or from the single chipxe2x80x94or a single fiber bundle could carry some signals to the chip and other away from the chip. The optical fibers are interconnected directly on top of or very close to the surface of the array. No bulk optics is needed and no fusing of images from separate transmitted and received arrays is required to get the two types of signals into the fiber bundle.
An object of the invention is an optoelectronic apparatus for transmitting and receiving digital data over fiber optics, comprising a silicon substrate with embedded electronic circuitry and a means of processing, a plurality of optical transmitters attached to the silicon substrate, a plurality of optical receivers attached to the silicon substrate, a plurality of optical fibers interconnecting the plurality of optical transmitters and the plurality of optical receivers on a first end, wherein a physical arrangement of the optical fibers at a second end correspond with a physical arrangement on the first end.
A further object is an optoelectronic apparatus, wherein the fiber optics individually interconnect to each transmitter and each receiver on the first end. Additionally, the plurality of optical fibers are subdivided into bundles, wherein the bundles connect to a plurality of optical devices. The bundles have a number of embodiments, including where some of the bundles are routed off the silicon substrate, some of the bundles are arranged in channels, some of the bundles connect to different topologies, some of the bundles comprise only transmitters, some of the bundles comprise only receivers, and wherein the bundles are routed to configure a desired architecture.
Another object of the invention is an optoelectronic apparatus for transmitting and receiving digital data over fiber optics, comprising a silicon substrate with embedded electronic circuitry and a processing means, a plurality of optical transmitters attached to the silicon substrate and grouped in a pattern, a plurality of optical receivers attached to the silicon substrate and grouped in a pattern, a plurality of optical fiber bundles which are independently, removably connectorized on the chip interconnecting the plurality of optical transmitters and the plurality of optical receivers on a first end through an image guide, wherein a physical arrangement of the optical fibers at a second end correspond with a physical arrangement on the first end.
An object of the invention includes an optoelectronic apparatus wherein the optical transmitters and the optical receivers have a number of different embodiments, including where the optical transmitters and the optical receivers are grouped interdigitated on the silicon substrate, the optical transmitters and the optical receivers are grouped in columns, the optical transmitters are grouped together, the optical receivers are grouped together, and where the embedded electronic circuitry and the processing means are physically separated from the optical transmitters and receivers.
A further object of the invention is a method of transmitting and receiving digital data over fiber optics, comprising the step of fabricating a silicon substrate with embedded electronic circuitry and a means of processing, attaching a plurality of optical transmitters to the silicon substrate, attaching a plurality of optical receivers to the silicon substrate, arranging the optical transmitters and the optical receivers in a pattern, interconnecting a plurality of optical fibers to the plurality of optical transmitters and the plurality of optical receivers on a first end.
Another object includes a method of transmitting and receiving digital data wherein the plurality of optical fibers interconnecting the plurality of optical transmitters and the plurality of optical receivers on a first end are physically arranged at a second end directly corresponding with a physical arrangement on the first end. Additionally, wherein the physical arrangement is a pattern that is interdigitated.
Yet an additional object is an optoelectronic apparatus for optically communicating with a plurality of network nodes, comprising a silicon substrate with embedded electronic circuitry with a plurality of optical emitters and/or detectors attached to the silicon substrate and electronically coupled to the embedded electronic circuitry. Multiple optical fibers are independently, removably connectorized onto the chip to interconnect the plurality of optical emitters and/or receivers with separate nodes of the plurality of network nodes. The plurality of emitters and/or detectors are physically grouped together in correspondence with the separate nodes of the plurality of network nodes to facilitate connection with the separate nodes over the multiple optical fibers respective of the separate nodes.
A further object includes the plurality of optical fibers subdivided into bundles of one or more optical fibers, with each bundle representing a separate node of the plurality of network nodes.
Another object is an optoelectronic apparatus wherein the plurality of emitters and/or detectors is configured to form a plurality of communication channels with one or more separate nodes of the plurality of network nodes. Additionally, wherein each of the plurality of communication channels is configured to communicate data in either one or both directions with the one or more separate nodes.
And yet an additional object is an optoelectronic apparatus, wherein the plurality of optical fibers are subdivided into bundles of one or more optical fibers with each bundle representing a separate node of the plurality of network nodes. And further, wherein individual ones of emitters are physically located next to individual ones of detectors to facilitate two directional communications with a separate node over a single optical fiber or bundle of optical fibers.
An object includes an optoelectronic apparatus wherein the embedded electronic circuitry includes digital logic circuitry for processing data received by a first detector over a first optical fiber prior to retransmission by the apparatus through a first emitter over a second optical fiber. And, wherein the first detector and the first emitter are separately located from each other on the silicon substrate to allow connection of the first and second optical fibers.
Finally, an optoelectronic apparatus wherein the first detector includes a plurality of detectors and the first emitter includes a plurality of emitters.
Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the detailed description, wherein we have shown and described only a preferred embodiment of the invention, simply by way of illustration of the best mode contemplated by us on carrying out our invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention.